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DHWCtrl.SpiActivate
Apply the pin routing described by PinMap and bring up
the SPI master on PeripheralIndex with the requested
clock, mode, and bit order. Word size is fixed at 8 bits. The
controller drives only SCK/MOSI/MISO; chip-select is not
managed here - drive it as an ordinary GPIO via GpioConfigure /
GpioSetState, and poll a BUSY/IRQ line via
GpioWaitState where the target requires it.
Properties
- Command code: 0xE140
- Command timeout: 100 ms
- Possible status codes: General status codes, DHWCtrl.ErrInvalidIndex, DHWCtrl.ErrAlreadyActive, DHWCtrl.ErrInvalidParam, DHWCtrl.ErrHardware
Parameters (request frame)
| Name | Type/Size | Description | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Length of PinMap | Integer (8 bits) |
Number of elements in the PinMap array |
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| PinMap | Array | Logical-to-physical pin assignments for this master (SpiSck / SpiMosi / SpiMiso; chip-select is a plain GPIO and is not part of the map). Must contain exactly the functions this instance requires; unknown, surplus, or duplicate names are rejected with ErrInvalidParam. | |||||||||||||||||
| Entry.Name | Enumeration (8 bits) |
Logical peripheral function this pin carries.
Logical pin-function identifier, prefixed by electrical bus/signal family (not by DHWCtrl peripheral category). A signal shared by 2 roles on the same bus reuses a single keyword - e.g. UsbDp / UsbDm serve both a USB host and a (future) USB device role. It is used as the logical side of a DHWCtrlPinMapEntry; a given Activate accepts only the names of the one or more buses its category uses. Values (24):
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| Entry.Pin.Port | Enumeration (8 bits) |
GPIO bank letter (A..Z).
SoC-native GPIO bank identifier. The keyword letters mirror the bank designators on STM32-style parts; not every part implements the full A..Z range. The firmware rejects banks it doesn't support with ErrInvalidParam. Values (26):
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| Entry.Pin.Number | Integer (8 bits) | Pin number within the bank. Practical range is SoC-specific (typically 0..15 on STM32). Named Number rather than Index to avoid a NameChecker collision with the peripheral-instance Index in ListPeripherals's Pins array (struct parents don't currently participate in field-name namespacing). | |||||||||||||||||
| PeripheralIndex | Integer (8 bits) | Zero-based instance index within this peripheral category; defaults to 0 (the first instance). The valid range is firmware/hardware-variant specific; discoverable via ListPeripherals. | |||||||||||||||||
| Settings.ClockHz | Integer (32 bits) |
SPI clock frequency in Hz. The firmware rounds down to
the nearest achievable prescaler value. Keep this within
the maximum clock frequency supported by the connected
target.
(Minimum value: 1) |
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| Settings.Flags | Bit mask (8 bits) |
Clock polarity and phase. Cpol occupies bit 1 and
Cpha bit 0, so the numeric value of this field is
exactly the conventional SPI mode number quoted by most
datasheets:
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| RFU | Integer (bit mask area 0xFC) |
Zero padding |
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| Cpol | Enumeration (bit 0x02) |
Clock polarity: the level the clock rests at while idle.
Values (2):
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| Cpha | Enumeration (bit 0x01) |
Clock phase: which clock edge of a bit period samples the data.
Values (2):
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| Settings.BitOrder | Enumeration (8 bits) |
Bit transmission order on the wire.
Values (2):
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Returned values (response frame)
None