Reference Manual

Access Restricted

This page contains internal documentation that is not publicly available.


DHWCtrl.SpiActivate

Apply the pin configuration named Pinset and bring up the SPI master on Index with the requested clock, mode and bit order. Word size is fixed at 8 bits. The controller drives only SCK/MOSI/MISO; chip-select is not managed here - drive it as an ordinary GPIO via GpioConfigure / GpioSetState, and poll a BUSY/IRQ line via GpioWaitState where the target requires it.

Properties

Parameters (request frame)

Name Type/Size Description
Index Integer (8 bits) Zero-based instance index within this peripheral category. The valid range is firmware / hardware-variant specific; discoverable via ListPeripherals.
Pinset Enumeration (8 bits) Ordinal index into the firmware's per-peripheral pinset array (mirrors a pinctrl-names entry). The valid set per peripheral instance is discoverable via ListPeripherals.
Values (8):
  • Pinset0 (0x00)
  • Pinset1 (0x01)
  • Pinset2 (0x02)
  • Pinset3 (0x03)
  • Pinset4 (0x04)
  • Pinset5 (0x05)
  • Pinset6 (0x06)
  • Pinset7 (0x07)
Settings.ClockHz Integer (32 bits) SPI clock frequency in Hz. The firmware rounds down to the nearest achievable prescaler value. Keep this within the maximum clock frequency supported by the connected target.
(Minimum value: 1)
Settings.Flags Bit mask (8 bits) Clock polarity and phase. Cpol occupies bit 1 and Cpha bit 0, so the numeric value of this field is exactly the conventional SPI mode number quoted by most datasheets:
CpolCphaSPI mode
IdleLowSampleOnFirstEdge0
IdleLowSampleOnSecondEdge1
IdleHighSampleOnFirstEdge2
IdleHighSampleOnSecondEdge3
RFU Integer (bit mask area 0xFC) Zero padding
Cpol Enumeration (bit 0x02) Clock polarity: the level the clock rests at while idle.
Values (2):
  • IdleLow (0x00)
    Clock idles low.
  • IdleHigh (0x01)
    Clock idles high.
Cpha Enumeration (bit 0x01) Clock phase: which clock edge of a bit period samples the data.
Values (2):
  • SampleOnFirstEdge (0x00)
    Each bit is sampled on the first clock edge of its bit period.
  • SampleOnSecondEdge (0x01)
    Each bit is sampled on the second clock edge of its bit period.
Settings.BitOrder Enumeration (8 bits) Bit transmission order on the wire.
Values (2):
  • MsbFirst (0x00)
    Most-significant bit of each byte first.
  • LsbFirst (0x01)
    Least-significant bit of each byte first.

Returned values (response frame)

None